In semiconductor integrated circuit memories, both static and dynamic, memory calls are typically accessed by charging a row line which is connected to a plurality of access transistors for the memory cells. Each of the access transistors presents a capacitive loading on the row line. The row lines are typically polysilicon and offer a significant impedance to the charging signal. It can be seen that as semiconductor memories become larger more power is required to drive the row lines due to increased capacitive loading as well as the resistance of the row line itself, if the cycle time of the memory is not to be reduced.
It has typically been the approach to this problem to fabricate a bigger driver circuit with more and large transistors for handling the greater load. This, however, presents more problems since, with more dense circuits and smaller geometries, less room is available for row driver circuits. Further the larger driver circuits themselves require more powerful decoder and buffer circuits which again increases the power and area of the integrated circuit.
Therefore, in view of these problems, there exists a need for a row driver circuit for static and dynamic memories wherein the problems of capacitive loading, excessive power consumption and access time are overcome.